1. Field of the Invention
The present invention relates to the field of integrated circuits. More particularly, it relates to a column redundancy system for use with a dynamic random access memory (DRAM) operating in a prefetch mode.
2. Description of the Related Art
Technological advances have permitted semiconductor integrated circuits to fit significantly more circuit elements in a given silicon area. Reducing and eliminating defects in the circuit elements has, however, become increasingly more difficult with the increased density of circuit elements. To achieve higher population capacities, circuit designers strive to reduce the size of the individual circuit elements to maximize available die real estate. The reduced size makes these circuit elements increasingly susceptible to defects caused by material impurities during fabrication. Nevertheless, the defects are identifiable upon completion of the integrated circuit fabrication by testing procedures, either at the semiconductor chip level or after packaging.
Scrapping or discarding defective integrated circuits when defects are identified is economically undesirable, particularly if only a small number of circuit elements are actually defective. In addition, relying on zero defects in the fabrication of integrated circuits is an unrealistic option. Therefore, redundant circuit elements are provided on integrated circuits to reduce the number of scrapped integrated circuits. If a primary circuit element is determined to be defective, a redundant circuit element is substituted for the defective primary circuit element. Substantial reductions in scrap are achieved by using redundant circuit elements without substantially increasing the cost of the integrated circuit.
One type of integrated circuit device that uses redundant circuit elements is integrated memory circuits, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), video random access memories (VRAMs), and erasable programmable read only memories (EPROMs). Typical integrated memory circuits comprise millions of equivalent memory cells arranged in arrays of addressable rows and columns. The rows and columns of memory cells are the primary circuit elements of the integrated memory circuit. By providing redundant circuit elements, either as rows or columns, defective primary rows or columns can be replaced.
Because the individual primary circuit elements (rows or columns) of an integrated memory circuit are separately addressable, replacing a defective circuit element typically comprises blowing fuse-type circuits to "program" a redundant circuit element to respond to the address of the defective primary circuit element. This process is very effective for permanently replacing defective primary circuit elements.
In the case of DRAMs, for example, a particular memory cell is selected by first providing a unique row address corresponding to the row in which the particular memory cell is located and subsequently providing a unique column address corresponding to the column in which the particular memory cell is located. When the address of the defective primary circuit element is presented by the user, redundancy circuitry must recognize the address and reroute all signals to the redundant circuit element.
During testing of the DRAM at the factory, defective primary circuit elements are identified and a suitable redundant circuit element is selected. The fuses corresponding to the redundant circuit are blown in a predetermined order to represent the address of the defective primary circuit element to be replaced. During each memory access, each address provided to the DRAM by the user is compared to the corresponding fuses to determine if a redundant match is present. Whenever a redundant match is detected, the primary circuit element is bypassed and the redundant circuit element is activated to perform the required function. Various techniques and redundant compare circuits are known in the art to facilitate the address/fuse compare operation. Exemplary compare schemes are described in U.S. Pat. No. 5,574,689 to Morgan, the entire content of which is incorporated herein by reference.
When an integrated memory circuit (e.g., a DRAM as described above) is operated in a prefetch mode, it simultaneously accesses multiple columns (i.e., multiple addresses) in a given clock cycle or series of clock cycles. For example, when a DRAM is operated in a 2-bit prefetch mode, it simultaneously access two columns (i.e., 2 addresses), thereby fetching two bits of data for every address specified by the user rather than one. That is, the user supplies a first address, and the second address is calculated internally by the DRAM. For each clock cycle (or series of clock cycles), the DRAM simultaneously accesses the first address (supplied by the user) and a second address (calculated by the DRAM). Of course, it should be understood that prefetch modes may be configured to simultaneously fetch more than two addresses. For example, a 4-bit prefetch will fetch four addresses at a time and an 8-bit prefetch will fetch eight addresses at a time, and so on. For purposes of simplicity, however, only the 2-bit prefetch will be described in connection with the invention.
The calculation of the second (or some greater number) address is conventionally carried out with an adder in the redundancy compare path of the column address path. Referring to FIG. 1, a primary circuit element address (e.g., a starting column address) is input by the user and is forwarded to a latch 100 for temporary storage. The primary circuit element address (e.g., column address) is then forwarded to a first redundancy compare circuit 120 over communication link 160, where it is compared with the addresses of redundant circuit elements located in the fuse sets 150 (e.g., as determined by the pre-blown fuses). If a match is detected between the user supplied address of the primary circuit element and an address of a redundant circuit element within the fuse sets 150, then a "Redundancy Enable" signal goes, e.g., logic HIGH and the primary circuit element (e.g., column) sought to be accessed is bypassed while the redundant circuit element (e.g., redundant column) is activated to perform the desired function (e.g., a memory access).
Simultaneously with the activation, the address is forwarded to an adder 110 over communication link 170, where a second address is calculated by the DRAM. The second address may be, e.g., an address adjacent to the starting column address. Assuming, for exemplary purposes, the user specified an address having a value of "1." In order for the DRAM to access a second (adjacent) address, the adder 110 adds "1" to the value of the specified address, thereby calculating the second address (e.g., value "2"). After the adder 110 has calculated the second address (e.g., value "2") it must be compared with the fuse sets 150 to determine if the second address ("2") matches a redundant address. To accomplish this, the second address is forwarded to a second redundant compare circuit 130 and is compared with the redundant addresses in the fuse sets 150 as described above.
One problem associated with the FIG. 1 configuration is that during the prefetch operation, the adder 110 is required to calculate the second address. Since the adder is located in what is known as the "speed path" (i.e., the column address path), and since the adder 110 requires time to calculate the second address, which is then forwarded to redundancy compare circuit 130, the entire memory access operation is slowed down.
The problem is exacerbated for prefetch operations of greater values (e.g., 4-bit, 8-bit, etc.) since more than one adder 110, 140, 160 must be used to calculate the multiple addresses, which are then forwarded to respective redundancy compare circuits 130, 170, 180 (e.g., for 4-bit prefetch). The addition operations increase the time required to perform the memory access, thereby greatly reducing the benefit of operating under a prefetch mode. Thus, there exists a desire and need for a redundancy system that may be used with an integrated memory circuit operating under prefetch mode that does not prolong memory access time.